The present disclosure relates to non-volatile storage.
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the drain and source diffusion regions. A control gate is provided over and insulated from the floating gate. The threshold voltage (VTH) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its drain and source is controlled by the level of charge on the floating gate.
Groups of memory cells may be associated with a bit line. In one approach, memory cells are arranged as NAND strings, with each NAND string being associated with one bit line. A selected memory cell in the group may be sensed by applying a voltage to the selected memory cell and sensing a signal on the bit line. During programming, different voltages can be applied to the bit line to control the rate at which the selected memory cell programs.
Typically, a program voltage VPGM applied to the control gate is applied as a series of pulses that increase in magnitude as programming progresses. In one possible approach, the magnitude of the pulses is increased with each successive pulse by a predetermined step size, e.g., 0.2-0.4 V. In the periods between the program pulses, verify operations are carried out. That is, the programming level of each element of a group of cells being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which the element is being programmed.
Typically, in addition to the data being programmed an Error Correction Code (ECC) that has been calculated from the user data is also stored. When the data is read back, the ECC is also read back. The ECC allows a certain number of misreads to be corrected even if it is not known which memory cells were misread. However, if there are too many misreads, then the ECC will be unable to correct the data. By storing more bits in the ECC, the recovery process can be made more robust. That is, more misreads can be corrected. However, this has the disadvantage of using additional memory cells to store the ECC.